Sampling circuit

ABSTRACT

A sampling circuit for sequential sampling of a broadband periodic input signal having a field effect transistor as a nonlinear component to which a pulsed-shaped sampling signal is supplied, by which sampling is activated so that an output signal is produced. In this way, a sampling circuit is attained which is economical, technically durable and which can be used in a versatile and simple manner.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a sampling circuit for sequential sampling of a broadband periodic input signal, there being a nonlinear component to which a pulsed-shaped sampling signal is supplied, by which sampling is activated so that an output signal is produced.

2. Description of Related Art

The detection of a broadband signal or a signal characteristic which changes quickly in time can only be done by means of real time sampling with very great technical effort or not at all. A typical application is fill level measurement by means of a pulsed radar, the technical problem lying in measuring the propagation delay of the radar signal very accurately. For distance measurement accuracy of 1 mm, accuracy of time measurement of roughly 6 ps is necessary. One possible alternative for real time sampling is sequential sampling. Sequential sampling manages with a much smaller sampling rate, but is limited solely to use for periodic signals. In contrast to real time sampling, only one sampling value is recorded per signal period. Then, a high speed signal to be sampled is reconstructed from a plurality of individual sampling points. Since this sampling process results in frequency conversion of the input signal, this process can also be interpreted as harmonic mixing.

One conventional implementation of a sampling circuit is shown in FIG. 1. An input signal to be sampled is routed via a transmitting and receiving line to two switching diodes 2, 3 arranged anti-parallel. The two switching diodes 2, 3 arranged anti-parallel are operated in the idle state by a respective DC bias applied first in the reverse direction. During the actual sampling process, a pulse-shaped sampling signal s₁(t) and a sampling signal s₂(t) which is inverse to it conductively switch the switching diodes 2, 3 so that the segment between the feed of the input signal u_(c)(t) to be sampled and the two sampling capacitors 4, 5 connected downstream of the switching diodes 2, 3 become low-resistance for a short time. The charging portion on the sampling capacitors 4, 5, which originates from the pulse-shaped sampling pulses, can discharge via the resistors 6, 7. Under the assumption that the sampling capacitors 4, 5 are filly discharged between the two sampling processes, the sampling points of the sampled input signal arise fundamentally from the average voltage u_(s)(t) prevailing over the sampling capacitors 4, 5. If the relationship s₁(t)=−s₂(t) applies between the two sampling signals, the nodes 8, 9 can be regarded as virtual ground points with respect to these signals. Consequently, in the ideal case, the sampling signals on these nodes 8, 9 are mutually cancelled out so that feedthrough of the sampling signals in the intermediate frequency path and the signal path is stopped, by which balancing of the circuit is achieved.

The disadvantages in this conventional approach are, among others, the extreme demands on the phase and amplitude characteristic of the two sampling signals which are inverse to one another, as are necessary for operational balancing. To ensure balancing, the two sampling signals must be identical according to absolute value, and at the same time, must have phases turned exactly 180°; this allows generation of these signals to become accordingly complex and makes the operation of the circuit susceptible to component tolerances.

SUMMARY OF THE INVENTION

In view of the above noted problem, it is a primary object of the present invention to devise such a circuit which is economical, technically durable and which can be used in a versatile and simple manner.

Proceeding from the initially described sampling circuit for sequential sampling of a broadband periodic input signal, this object is achieved by there being a field effect transistor as a nonlinear component.

Therefore, in accordance with the invention, a field effect transistor is used to activate sampling, so that, when a pulse-shaped sampling signal is present, to detect the input signal to be sampled, and thus, to produce the output signal as a sampled signal. Here, it holds that the field effect transistors have inherent decoupling between the gate and drain so that, for suitable connection of the field effect transistor, the sampling signal crosses neither into the signal path nor into the intermediate frequency path. Another advantage of a sampling circuit with a field effect transistor lies in the inherent noise balancing, since the signal at the gate is not rectified.

Altogether therefore, inherent decoupling of the trigger signal and the output signal with inherent noise balancing of the sampling circuit is obtained. The selection of different types of field effect transistors (n-channel/p-channel) yields other degrees of freedom with respect to the polarity of the unipolar sampling pulses and the implementation of different output impedances for the sampled input signal.

Basically, there are various possibilities for feeding of the input signal or of the sampling signal. According to one preferred development of the invention, it is provided that feed of the input signal takes place on the drain contact of the field effect transistor. According to a preferred development of the invention, it is further provided that there is a feed of the sampling signal on the gate contact of the field effect transistor.

According to a preferred development of the invention, there is also decoupling of the output signal on the drain contact of the field effect transistor. Furthermore, it is preferably provided especially that the feed of the input signal is separated from decoupling of the output signal by means of a filter arrangement. Preferably, on the feed side, a high--pass filter is used and/or on the decoupling side a low--pass filter is used. A multistage LC filter with magnetically shielded inductances is especially preferred.

According to another preferred development of the invention, it is provided that decoupling of the output signal on the source contact of the field effect transistor takes place. Preferably, the drain contact of the field effect transistor is DC-decoupled via a capacitance. Moreover, it is preferably provided that the input signal is supplied to the field effect transistor via a transmitting and receiving line into which a II-attenuation element is inserted. Furthermore, on the decoupling side, there is preferably a filter arrangement, quite especially in the form of a RC filter cascade. Finally, there is preferably another storage capacitor on the decoupling side.

In the preferred development of the invention described last, there can be an additional field effect transistor connected as a “dummy.” In this way, a circuit structure is obtained which constitutes an expansion of the above described circuit. More or less, it is two individual circuits of identical structure, with one field effect transistor each, the output signal of the entire circuit being formed from the difference of the intermediate frequency signals of the two individual circuits. While one individual circuit is made and operated as is described above, the field effect transistor of the additional individual circuit is connected as a “dummy”. The drain contact of the additional field effect transistor is loaded with an impedance which is preferably identical to the load impedance, by which the other field effect transistor is loaded on the drain contact by the signal path. Furthermore, it can be preferably provided that the two field effect transistors are supplied with the same sampling signal. Moreover, it is preferably provided that the two field effect transistors are triggered with the same gate bias.

In particular, there are now a plurality of possibilities for embodying and developing the sampling circuit of the invention for sequential sampling of a broadband periodic input signal. For this purpose, reference is made to the following detailed description of preferred embodiments of the invention along with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional sampling circuit based on diodes connected anti-parallel,

FIG. 2 is a block diagram of a first preferred exemplary embodiment of the present invention,

FIG. 3 is a block diagram of a second preferred exemplary embodiment of the present invention, and

FIG. 4 is a block diagram of a third preferred exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The sampling circuits described below, according to preferred exemplary embodiments of the invention, each have GaAs junction gate field effect transistors with Schottky contacts which are passively operated, i.e., without stipulation of a drain-source voltage. In addition to very good, large signal properties, absolute stability of the circuit can be achieved in this way, The actual sampling or frequency conversion of a broadband input signal u_(c)(t) to a narrowband intermediate frequency signal u_(s)(t) takes place by modulation of the nonlinear, voltage-dependent drain-source channel resistance by means of a pulse-shaped sampling signal s(t).

FIG. 1 shows a sampling circuit according to a first preferred embodiment of the invention. The input signal to be sampled is supplied to the sampling circuit via a transmitting and receiving line 10. The input signal to be sampled is injected via the drain contact I 1 of a field effect transistor 12. The sampling signal s(t) is sent to the gate 13 of the field effect transistor 12. In combination with an applied DC bias U_(DC), the sampling signal thus periodically controls the channel resistance of the drain-source section, with which the working point for the input signal u_(c)(t) to be sampled is determined. The DC working point of the field effect transistor 12 is generally selected via the bias applied to the gate contact 13 such that, in combination with the sampling signal supplied via a capacitor 14, modulation of the channel between the closed and open channel takes place.

Furthermore, by choosing the DC bias and the polarity of the pulses of the sampling signal in combination with the channel doping of the field effect transistor 12, the impedance of the drain-source section which is average in time, and thus, the output impedance of the circuit can be determined. If the gate 13 of the field effect transistor 12 is, for example, negatively biased in the n-doped channel and the polarity of the sampling signal is selected to be positive, the drain-source section is low-resistance only during the interval of the short pulses of the sampling signal, and thus, is high-resistance averaged over time, here, in the range of several Kohms.

On the other hand, a slightly positive DC bias in combination with negative pulses of the sampling signal, averaged over time, causes relatively low-resistance impedance of the drain-source section in the range of a few ohms. The polarity selection of the triggering of the circuit and the associated determination of the output impedance does not directly affect the efficiency of the circuit, but depends rather on the intended application. An implementation with a low-resistance output impedance, for example, enables a roughly DC-free output signal in spite of the possibly required DC-coupled decoupling of the intermediate frequency signal, since, over the low-resistance channel resistor, a storage charge cannot build up which would then be superimposed on the intermediate frequency signal as the DC portion.

The input signal u_(c)(t) to be sampled is fed and the sampled signal, therefore the output signal U_(s)(t), is decoupled on the drain contact 11 of the field effect transistor 12. Here, the two signals are separated from one another by a filter arrangement 15. On the side of feed of the input signal, there is specifically a high-pass filter 16 and on the side of decoupling of the sampled signal there is a low-pass filter 17. Here, the use of a multistage LC filter which has only magnetically shielded inductances is recommended in order to suppress possible magnetic coupling at this circuit point.

FIG. 3 shows a sampling circuit according to a second preferred exemplary embodiment of the invention. By a slight modification of the structure of the circuit as compared to the first preferred exemplary embodiment of the invention, the required filter While the drain contact 11 of the field effect transistor 12 without a filter is directly in the transmitting and receiving path, there is tapping of the output signal on the source contacts 18 of the field effect transistor 12. In this preferred embodiment of the invention, a II-attenuation element 19, which is used to improve the input matching of the circuit, is installed in the transmitting and receiving line.

If, as described above, the bias on the gate 13 of the field effect transistor 12 is selected to be negative and the polarity of the pulses of the sampling signal to be positive, for the duration of the pulse of the sampling signal, the channel resistance of the drain-source section becomes low-resistance, so that a storage capacitor 20 connected to the source contact 18 is charged to a fraction of the instantaneous voltage of u_(c)(t). For the remaining time of the sampling period, the channel is high-resistance so that intermediate frequency tapping of the input signal u_(c)(t) which is to be sampled is isolated. To further suppress the small higher frequency signal portions superimposed on the intermediate frequency signal on the source contact, a simple RC filter cascade 21 is used. In RC filters, it is advantageous that they are insensitive to incident magnetic and electrical radiation, in contrast to LC filters, so that injection of noncoherent signals is prevented.

FIG. 4 describes a sampling circuit according to a third preferred exemplary embodiment of the invention. Here, it is more or less an expansion of the circuit shown in FIG. 3 according to the second preferred embodiment of the invention, there being an additional field effect transistor 22. This circuit with two field effect transistors 12, 22 is composed of two individual circuits of identical structure, the output signal of the entire circuit being formed from the difference of the intermediate frequency signals of the two individual circuits, for which there is a difference amplifier 27. The upper individual circuit of the entire circuit according to the third preferred exemplary embodiment of the invention from FIG. 4 corresponds to the above described circuit from FIG. 3. The field effect transistor 22 of the bottom circuit is, however, connected as a “dummy.” This means that the drain contact 23 of the additional field effect transistor 22 is loaded with an impedance 24 which is identical to the load impedance by which the field effect transistor 12 is loaded on the drain contact by the signal path.

In addition to the identical load-side connection of the field effect transistors 12, 22, the two circuits are triggered with the same sampling signal and the same gate bias. Graphically represented, this means that the pulses of the sampling signal travel beyond the two gates 13, 25 of the field effect transistors 12, 22 and are terminated without reflection with a terminating impedance. Due to the identical connection and triggering of the two field effect transistors 12, 22, the direct components in the intermediate frequency signals u_(s1)(t) and U_(s2)(t) of each circuit are likewise identical so that the DC-free intermediate frequency signal u_(s)(t) results from the difference u_(s1)(t)−U_(s2)(t). 

1. Sampling circuit for sequential sampling of a broadband periodic input signal, comprising: a nonlinear component to which a pulsed-shaped sampling signal is supplied, by which sampling is activated so that an output signal is produced, wherein the nonlinear component comprises a field effect transistor.
 2. Sampling circuit as claimed in claim 1, wherein an input signal feed is provided at a drain contact of the field effect transistor.
 3. Sampling circuit as claimed in claim 1, wherein a sampling signal feed is provided at a gate contact of the field effect transistor.
 4. Sampling circuit as claimed in claim 1, wherein an output signal is decoupled at a drain contact of the field effect transistor.
 5. Sampling circuit as claimed in claim 4, wherein an input signal feed is provided at a drain contact of the field effect transistor and is separated from decoupling of the output signal by a filter arrangement.
 6. Sampling circuit as claimed in claim 5, wherein a high-pass filter is provided on a feed side and a low-pass filter is provided on a decoupling side.
 7. Sampling circuit as claimed in claim 6, further comprising a multistage LC filter with magnetically shielded inductances.
 8. Sampling circuit as claimed in claim 1, wherein an output signal is decoupled at the source contact of the field effect transistor.
 9. Sampling circuit as claimed in claim 8, wherein a drain contact of the field effect transistor is DC-decoupled via a capacitance.
 10. Sampling circuit as claimed in claim 8, wherein the input signal is supplied to the field effect transistor via a transmitting and receiving line containing a II-attenuation element.
 11. Sampling circuit as claimed in claim S, wherein a filter arrangement is provided on a decoupling side.
 12. Sampling circuit as claimed in claim 11, farther comprising an RC filter chain.
 13. Sampling circuit as claimed in claim 8, wherein a storage capacitor is provided at a decoupling side.
 14. Sampling circuit as claimed in claim 8, further comprising a second field effect transistor connected as a dummy.
 15. Sampling circuit as claimed in claim 14, wherein a drain contact of the second field effect transistor is loaded with an impedance.
 16. Sampling circuit as claimed in claim 15, wherein the impedance with which the drain contact of the second field effect transistor is loaded is equal to an impedance with which the other field effect transistor is loaded on a drain contact.
 17. Sampling circuit as claimed in claim 14, wherein the field effect transistors are connected to receive the same sampling signal.
 18. Sampling circuit as claimed in claim 14, wherein the field effect transistors are connected so as to be triggered with the same gate bias.
 19. Sampling circuit as claimed in claim 14, wherein a sampling signal feed is provided at a gate contact of the field effect transistor, and wherein a terminating impedance is provided which terminates the feed of the sampling signal without reflection.
 20. Sampling circuit as claimed in claim 14, further comprising a difference amplifier connected to receive output signals of the field effect transistors. 